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 STS25NH3LL
N-channel 30 V - 0.0032 - 25 A - SO-8 STripFETTM III Power MOSFET for DC/DC conversion
Features
Type STS25NH3LL VDSS 30 V RDS(on) ID <0.0035 25 A (1)
1. This value is rated according to Rthj-pcb
Optimal RDS(on) x Qg trade off @ 4.5 V Conduction losses reduced Switching losses reduced
SO-8
Applications
Switching applications
Figure 1.
Internal schematic diagram
Description
This device utilizes the advanced design rules of ST's proprietary STripFETTM technology. The innovative process coupled with unique metallization techniques makes it possible to produce the most advanced low voltage Power MOSFET in an SO-8 package. The device is therefore suitable for demanding DC-DC converter applications where high efficiency at high output current is needed.
Table 1.
Device summary
Marking 25H3LL Package SO-8 Packaging Tape & reel
Order code STS25NH3LL
November 2007
Rev 10
1/11
www.st.com 11
Electrical ratings
STS25NH3LL
1
Electrical ratings
Table 2.
Symbol VDS VGS ID(1) ID IDM(2) PTOT
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C Value 30 18 25 18 100 3.2 Unit V V A A A W
1. This value is rated according to Rthj-pcb 2. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-pcb (1) Tj Tstg
Thermal data
Parameter Thermal resistance junction-amb max Operation junction temperature Storage temperature Value 47 -55 to 175 Unit C/W C
1. When mounted on FR-4 board of 1 inch, 2 oz Cu, t< 10 sec
Table 4.
Symbol IAV EAS
Avalanche characteristics
Parameter Not-repetitive avalanche current (pulse width limited by Tj max.) Single pulse avalanche energy (starting Tj = 25 C, ID = IAV, VDD = 24 V) Value 12.5 1.3 Unit A J
2/11
STS25NH3LL
Electrical characteristics
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating @125 C VGS = 18 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 12.5 A VGS= 4.5 V, ID= 12.5 A 1 0.0032 0.0035 0.004 0.005 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
Table 6.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd QOSS (2) RG
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Output charge Gate input resistance Test conditions VDS = 10 V, ID = 12.5 A VDS =25 V, f = 1 MHz, VGS = 0 VDD = 15 V, ID = 25 A VGS = 4.5 V Figure 14 VDD= 24 V, VGS = 0 f = 1 MHz, gate DC bias =0 test signal level = 20 mV open drain 1 Min. Typ. 30 4450 655 50 30 12.5 10 23 2 3 40 Max. Unit S pF pF pF nC nC nC nC
1. Pulsed: pulse duration=300 s, duty cycle 1.5% 2. QOSS = Coss * Vin, Coss = Cgd + Cds
3/11
Electrical characteristics
STS25NH3LL
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 15 V, ID = 12.5 A, RG= 4.7 , VGS = 10 V Figure 13 Min. Typ. 18 50 75 8 Max. Unit ns ns ns ns
Table 8.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 25 A, VGS = 0 ISD = 25 A, di/dt = 100 A/s, VDD = 25 V, TJ = 150 C Figure 18 32 34 2.1 Test conditions Min Typ. Max 25 100 1.3 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 s, duty cycle 1.5%
4/11
STS25NH3LL
Electrical characteristics
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
5/11
Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
STS25NH3LL
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
6/11
STS25NH3LL
Test circuit
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
7/11
Package mechanical data
STS25NH3LL
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
8/11
STS25NH3LL
Package mechanical data
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
9/11
Revision history
STS25NH3LL
5
Revision history
Table 9.
Date 19-Nov-2007
Document revision history
Revision 10 Changes Document status promoted from preliminary data to datasheet
10/11
STS25NH3LL
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